The present invention relates generally to integrated circuits and methods for their use. More specifically, the invention relates to an integrated circuit design which is capable of being configured to perform multiple roles by using different bonding patterns.
Integrated circuits (ICs) are fabricated for many different purposes. As IC fabrication technology progresses, application flexibility generally decreases; that is, the roles for which an IC is suitable decrease with increasing specificity of design. For purposes of economy and efficiency, it is often desirable to leave an IC's role options unspecified for as long as possible.
Various strategies for retaining the flexibility of ICs as late as possible in the fabrication process are presently in use. Many ICs are designed to perform multiple roles. FIG. 1 illustrates an example of one such design. FIG. 1 shows a portion of an IC 10 having a voltage source (V.sub.ss) 12 and a voltage drain (V.sub.DD) 14. A metal line 16 is connected either to V.sub.ss 12 via a metal line 18 formed on the IC, or to V.sub.DD 14 via a metal line 20, depending on the design requirements at hand. Control over which line prints is provided by using a particular mask or reticle during the metalization patterning step used to form that layer of the IC 10.
If the connection to V.sub.ss 12 is made via metal line 18, the circuit is initialized to a low logic value when the chip is powered-up. This low logic value is converted by an inverter 22 to a high logic value on line 24, which adapts the IC to a particular role. For instance, the IC may recognize a high logic value on line 24 as a signal that it should expect a 5 Volt (V) power supply, whereas a low logic level on line 24 could indicate a 3 V power supply to the IC. The second option may be specified by connecting circuit line 16 to V.sub.DD 14 via line 20, rather than to V.sub.ss 12 via line 18.
This IC design permits a level of flexibility by allowing a decision regarding the role of an IC to be implemented at some time after the initial fabrication stage. However, this design still requires that the IC role be specified at a relatively early stage in the IC manufacturing process (i.e., at the metalization patterning stage). It would be advantageous to retain this flexibility for as long as possible, in particular as far as the packaging stage. In this way, foundries might be able to specify multiple roles for an IC starting from the same basic wafer design, and thereby reduce starting wafer inventories and associated costs.
FIGS. 2A and 2B illustrate IC designs which permit the flexibility in the IC to be retained until a later stage in the manufacturing process than the design of FIG. 1. FIG. 2A shows a portion of an IC 100. The IC 100 comprises a random access memory (RAM) bit 101 connected to a voltage source (V.sub.ss) 102 and a voltage drain (V.sub.DD) 104. Interposed between V.sub.ss 102 and V.sub.DD 104 are a p-channel transistor 106, and an EPROM (erasable-programmable read only memory) 108. The source of p-channel transistor 106 and the drain of EPROM 108 connect to the input of an inverter 112 through a line 110. The output of inverter 112 is connected to the remainder of the IC through a line 114.
Optional roles for this IC may be specified by programming the EPROM 108. When power is supplied to the chip, the IC attempts to bias the memory bit 101 to a high logic value with a negative bias, nINIT, applied to the gate of p-channel transistor 106. But when the EPROM 108 is programmed to be conductive, this high logic level is overcome by the ground connection to V.sub.ss 102 and the RAM bit is initialized to a low logic level. This low logic level is inverted by the inverter 112 to a high logic level, which adapts the IC to a particular role. For instance, the IC could interpret a high logic value on the RAM bit line 114 to indicate a 5 V power supply. Where the EPROM 108 is not conductive, the high logic value on line 110 is inverted to a low logic value by the inverter 112 and provided to the remainder of the IC, adapting it to an alternate role, such as 3 V operation. A fuse may also be used in place of the EPROM 108. The fuse could then be blown or left intact to specify the IC's role.
This design provides additional flexibility, since the same fabrication process can be used for ICs having the option of performing multiple roles. The EPROM may be programmed at the foundry during the testing of die on the wafers, for adaptation of the IC to the particular role intended by the user. The EPROM may even be programmed and reprogrammed by the user following receipt of the chip by normal EPROM erasing/programming methods.
FIG. 2B shows an alternate EPROM IC design. Memory bit 150 incorporates a latch 152 which provides a feedback mechanism for maintaining the logic values on either side of the inverter 154. This feedback latch 152 is combined with a POR (power-or-reset) switch (not shown) which triggers the p-channel transistor 156 to switch off, so that it no longer conducts once there is sufficient voltage for normal operation of the IC upon power-up. Thus, once the POR threshold is reached, the circuit no longer consumes power through p-channel 156. The IC's role-determining logic values are thereafter maintained by the latch 152, which comprises strong and weak inverters. The strong inverter 154 propagates the inverse of the input logic value to the remainder of the IC so that the IC role is set. The weak inverter 158 returns the input value to the initiation point so that both logic values are maintained.
When operating properly, this alternative EPROM structure of FIG. 2B provides an energy savings over the basic EPROM structure of FIG. 2A, since the p-channel transistor does not conduct and thus reduces the power consumption. However, POR varies with environmental and process conditions, and is sometimes difficult to determine. As a result, in normal operation POR can fluctuate, for instance, below the minimum voltage necessary for operation of the EPROM. In this instance, the POR switch can open to remove power from the IC before the proper role signal is generated and read. Under these circumstances, the device is defective. Accordingly, this energy-saving EPROM implementation may be unreliable.
Moreover, because EPROMs must be present in an array, they take up much more space on a chip than a discrete device would. EPROMs also require programming which increases the overhead associated with ICs which incorporate them.
Thus, there is a need for an improved IC design which maintains flexibility until as late as possible in the manufacturing process, in particular as late as the packaging stage. The design should ideally be compact, energy efficient and reliable.